basic logic gates lab report discussionbasic logic gates lab report discussion

Include these measurements within the Discussion Topics of your report. Then, we captured, the simulation waveforms for the report. These gates are the basis for building more complex logic circuits that are constructed using various combinations of gates, which is known as Combinational Logic. Using only four NAND gates, draw the logic circuit for NOR gate. A logic design that implements a full adder is shown below in Figure 1. Discussion NOT, OR and AND gates are the basic logic gates. HlSMs0+dI|Y#39D77e#q_xXZxjC\+|_ZsA\;,@pH $RLeJ&|~KGg5dBj^H`NLs%)#{,,t-FdV_6- v . Figure 5-4 Logic Circuit for part 1 .

Please see the online tutorial for instructions on how to use this software. f?3-]T2j),l0/%b WebThree logic gates can be compared to show how they differed in terms of their truth tables and output voltages. At any given moment, every terminal is in one of the two binary xref Use one of the CMOS NAND gates in a 4011 to verify its function and measure its propagation delay for both the rising edge and the falling edge using the same method as in the inverter experiment. These logic gates perform the basic Boolean functions, such as AND, OR, NAND, NOR, Inversion, Exclusive-OR, Exclusive-NOR. Now connect all the inputs of the remaining three NAND gates on the chip to the output and measure the propagation delay again. WebBasic Logic Gates X Objectives: The objectives of this experiment are to: 1. HV]oH}tff`(qhmG5TU+`5j~/={oX| \^zs.ujb ^?3Bk HH Q74&?eK\]E#xxr oQ2d1R.;PF?|J*`I" 0 1 0 0 1 1 Introduce students to the tools, facilities and components needed for the experiments in digital Therefore, there can be many ways to define the starting point and the finishing point of the transition process. Your algorithm will ask the user to provide the. 0000007396 00000 n Figure 1 below shows the schematic of our 1-Bit Adder design. Students should become familiar with these characteristics. Logic gates lab report By: Brenen Thayaparan Logic gates lab report By: Brenen Thayaparan Logic gates lab report By: Brenen Thayaparan 452600 TEJ3M0: Computer Technology Louise Arbour Secondary School Mr. Lowe 0000006629 00000 n 297 23 0000003695 00000 n NOT Gate 6 VII. 0000001719 00000 n Assume at the start of this sequence the variables are set as follows: List_Size = 5 Num-1 = 2 Num-2 = 6 Num-3 = 3 Num-4, algorithm (in pseudocode) for the following Scenario.

WebLab Report On Basics Logic Gate Uploaded by Shyam Kumar Description: basically this is physics lab report on basic logic gate Copyright: All Rights Reserved Available Formats Download as PDF, TXT or read online from Scribd Flag for inappropriate content Download now of 9 BASIC LOGIC GATES Shyam Kumar M.Sc Physics Roll No-15510059 xb```b``][ |,@Q <]>> Web7400 (NAND gate) 7402 (NOR gate) Discussion: NAND and NOR gates are two important gates because they are considered universal gates. 0000009339 00000 n After this creation was completely done and tested to, make sure it ran properly.

Web- To study the realization of basic gates using universal gates.

A Truth Table defines how a combination of gates will react to all possible input combinations. The OpenLab is an open-source, digital platform designed to support teaching and learning at City Tech (New York City College of Technology), and to promote student and faculty engagement in the intellectual and social life of the college community. hXn6>&X8f[%V

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endstream endobj startxref 02: 0000003362 00000 n 189 0 obj <> endobj The three AND gates that I mentioned above would have the inputs of, each input from the three. Try it.

DC noise is caused by a drift in the voltage levels of a signal. Note: results may vary we could find within our packaged IP block when creating the new project. gate type. Fig. endstream endobj 549 0 obj<>/W[1 1 1]/Type/XRef/Index[22 497]>>stream Implement Boolean functions using universal gates Generally speaking, the starting point of the transition process depends upon the threshold point of the gate in question, and the finishing point of the transition process depends upon the threshold point of the following gate.

The NAND gate is a universal gate because it can be used to produce the NOT operation, the AND operation, the OR operation, and the NOR operation. Why are NAND gates and NOR gates sometimes referred to as. 0000009525 00000 n other way around. TTL and ECL are based upon bipolar transistors.

for this example.

BHG&-xkb63->tL6m,e-\N7/PC}-X6u\HR'M,1``qw4ovA[r c7 q#\Dp6`u]vq*feow[o-CtC[A U%;7w~CHWw>w;qY()\7Eq0+B!^ ZXu^8Q?~|'p&?r%gL(ox`:/YKKs_(!Ha)k The experiment was also aimed at study of the behavior of the gates such as 74xx series TTL gates by using voltage range of 0 and +5. The power supply for TTL ICs usually is 5V. <]>> A complex electronic system may have many thousands of gates. Input B 0 1 0 1. It is made up of a p-type MOS transistor and a n-type MOS transistor. trailer However, this is not a required step for this lab. In practice, this is advantageous since 0000010276 00000 n

If you wish to confirm your prediction, repeat step 6 for the NOR gate. 1) Find the Boolean equation for the logic circuit shown in Figure 5-5. 2) Complete the Truth table (Table 5-3) and measure the voltages of VA, VB, VC, and VY for each input/output. if VDD = 5V, its noise margin is 2V).

It was aimed at examination of the basic logic gates such as AND, NAND, OR and NOR and comparison of the outputs to the truth table.

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0000008952 00000 n However, this lab will focus on tools that will

What do you observe? 0000003618 00000 n G^@r#Rd+jJFx :{n6nR!c:@M3vCc$@K:5c0vA#oQLf7WW7(;bDd|7. 0000008112 00000 n WebLAB #1 Introduction to Logic Gates LAB OBJECTIVES 1. Doing this lab will show us how to develop adder design as well as hierarchical design which. After performing this experiment, you will be able to use NAND and NOR gates to perform functions described by ANDs, ORs, and NOTs. ^Q(evs-A7Vs,)coRQ3d!d`@1( ^FeUx>b`8pi%E&]- 0000003116 00000 n WA word/_rels/document.xml.rels ( n0DbLPL6Ul[\-~v%!jbuXA9kGt @x{@uLVS(U~{|9\HKQ~-fcA/29?kV~p$6CyF"|~kk^*E*b6&|qPbu ~fWk @HBE`]p9O[W"8J!l/MJmQ 0 to 0.8V = Logic 0 and lights the L indicator. Course Hero is not sponsored or endorsed by any college or university. ?pn\}(n~~jA;8@'gNpB[hq\^(E=o}^ {*. Connect one of the inverters as shown in Fig. Before we could continue to part 2, we created an IP package that.

As those statements will play a major role in, comprehending advanced programming languages such as C++ and Javasccript. It was however, noticed that there is a You can construct all of the other basic gates using only NAND or only NOR gates. Webnot sufficient to implement complex digital logic functions. Table 5-1 Truth table and volts measured for input/output for Figure 5-4. Conclusion / Summary: Realization of Experiment (3) Conducting Experiment (3) Team Work (3) Data Collection (3) Data Analysis (3) Computer Use (3) Discipline and Precautions (2) Total Marks (20) Obtained Marks 231 0 obj <>stream 0000004000 00000 n WebBasic Logic Gates X Objectives: The objectives of this experiment are to: 1. Repeat steps 2 11, with the other Logic gates (integrated chips), and change each circuit according to the each individual lab. Write truth table in the space provided below: ##### LAB TASK#2: For the logic circuit given below do the following: i. 1) Find the Boolean equation for the logic circuit shown in Figure 5-4. Row (i) shows the name of the gate, row (ii) shows the electronic symbol, row (iii) shows the logic expression and row (iv) shows the truth table. Procedure: Explain your result. As those The basic logic gates are the basic building blocks of more complex logic circuits.

0000003627 00000 n Assume at the start of this sequence the variables are set as follows: List_Size = 5 Num-1 = 12 Num-2 = 8 Num-3 = 5 Num-4. Likewise, an OR gate is typically implemented as a NOR gate followed by an inverter not the

For example, a standard TTL gate will have a noise margin of 1V, whereas a CMOS gate has a noise margin of 40% of the supply voltage (i.e. The NAND and NOR gates are universal gates. 210 0 obj <>/Filter/FlateDecode/ID[<35808AB13E2D994C9570C98E011FA0A5><169F4C793813C04FB74B8734F5BF8F1F>]/Index[189 43]/Info 188 0 R/Length 100/Prev 284896/Root 190 0 R/Size 232/Type/XRef/W[1 2 1]>>stream

We see some defects as the logic is settling, like tiny spikes, but it eventually settles to the same value as your behavioral simulation. Web#VHMankar #DigitalElectronics #Lab #VirtualLab #MSBTEThe lab work for performing verification of basic gates are explained here using IC 7408, 7432, 7404 etc. Draw the circuit for the expression of XNOR Gate using basic gates. 0000008399 00000 n Noise margin is the maximum noise voltage added to the input signal of a digital circuit that does not cause an undesirable change in the output. Observe the output on a scope. The former has a wide operating-temperature range, suitable for military use, and the latter has a narrower temperature range, suitable for industrial use. B|,f>~pF20]oC `5o`"n`rtl R"[/X6d6d/ZFG&{A#e]G&yl+:e*Q(DJY *pNzPP=080:pvYgav E}Xs~9]m s~IkTlFD>+cb_R7(#TrpF ,2A}bi@x6t%)@-w TTL has a well-established popularity among logic families. WebLab Report: Digital Logic Lab Report: Digital Logic Introduction Gates-----At the most basic level, gates are simply electronically controlled switches. i - >$ublIoX&,3jYfDP76iB%l4e/+[. ciJyYH_PVb53](ZmBFAS~B`k:e5[WUx5e,e(L,GC ,]GW= lx(p% We ran, the simulation and analyzed the results to make sure our adder has proper functionality. WebA logic gate is an elementary building block of a digital circuit. 0000001929 00000 n 0000011065 00000 n How many inverters could be formed using a 7400 NAND IC. Use one of the transmission gates in a 4066, and connect a 50Hz unipolar input (0V5V) to its control pin and a bipolar 1KHz square wave to its input pin.

3) Reconstruct the circuit above using only NAND gates. Fig.

We had to create a logic design according to the instructions. 519 0 obj<> endobj The Cin input will be the carryout bit. End of preview. This particular lab will require us, to work on a 1-bit adder. Invalid logic voltage levels light neither indicator. Web12. Draw a truth table to verify the function. An inverter can be made from a NAND gate by connecting all of the inputs together and creating, a single input as shown below.

xbba`b``3 1` U Want to read all 7 pages. 0000004589 00000 n 3 shows a CMOS inverter circuit. biXAD`M G@ 1`8u:=2$ @#HF @ N 0 This will require us to make a design that looks like the one within the, instructions (Figure 2). WebTo verify logic truth tables from the voltages measured.

IC digital logic families. Suppose logic 0 is 0V and logic 1 is 5V, ideally. 1 that each gate has one or two binary inputs, X1 and X2, and one binary output, Z. Now that you are able to use the NAND and inverter, use them to construct an AND gate. WebLAB REPORT Discussion of Results 1. Output (LED) 0 0 0 1. Nguyen Quoc Trung. In practice, NAND and NOR gates are economical and easier. basic gates; we can create any logic gate or any Boolean expression by combining them. Include Boolean algebra, truth tables, and logic diagrams for the circuit reconstructed with only NOR gates. WebBasic Logic Gates. The students must save the screenshots each circuit to create a power of CSIS Logic. Course Hero member to access this document, Cavite State University Main Campus (Don Severino de las Alas) Indang, United States International University (USIU - Africa), Cavite State University Main Campus (Don Severino de las Alas) Indang CPEN 21A, United States International University (USIU - Africa) APT 2020, CUNY New York City College of Technology EMT 1250, Alightle_ResearchImprovementIdeas_11192018.docx, Vaughn College of Aeronautics and Technology, Stepping Stone Lab Three - Branches Reflection.docx, Rasmussen College, Florida HIM 141 HIM 12, Vaughn College of Aeronautics and Technology FLT 241, Southern New Hampshire University IT 511, Purdue University, Northwest MGMT ORGANIZATI, Southern New Hampshire University QSO 345, 07 01 DEANlNG CORRELATIO NAL AND DIFFERENTIAL RESEARCH METHODS 147 this prove th, 16 In Zimbardos Stanford Prison Experiment young psychologically normal men were, Diet Description Issues Cabbage Soup Diet Lemon Detox Macrobiotic Diet Raw Food, Fall Prevention in Healthcare Settingsxx.docx, AI Neural network basics - Elements of AI.pdf, 8 3315 Trial test 9 Written final exam Module Basic Mathematics General Stenden, 85 The LEAD program was initiated in 2011 with objective of reducing criminal, Question 4 What is Petes first decision as president of the company Selected, PC1 module 7 In vitro assays in preclinical DD.docx, Example of Binomial Distribution Example of Binomial Distribution Martin, Terminale Bac Pro suites numriques squence.doc, Run through the following sorting algorithm and determine the largest number.

The power supply for CMOS ICs ranges from 3V to 15V. NAND Gate 8 IX. There are various commercial integrated circuit chips available. 0 1 1 0 0 0 All seven basic logic gates have different rules for their truth table. 0000001112 00000 n Then the signals travel through a series of gates, the sum of the propagation delays through the gates is the total propagation delay of the circuit. %PDF-1.5 % 0000019247 00000 n Looking within the library, we do not have this, option. CMOS logic consumes far less power than MOS or bipolar logic.

%PDF-1.5 % The X input will be bit where it will be one of the two binary numbers being added.Also, the Y input will be bit where it will be one of the two binary numbers being added as well. Then it shows, in the instruction we have to create a 3 input XOR gate. Figure 5-1 An inverter operation generated by the use of NAND gate, Figure 5-2 An AND operation generated by the use of two NAND gates, Figure 5-3 An OR operation generated by the use of three NAND gates. AC noise is a random pulse that may be created by other switching signals. Simulation of the circuit in Figure F3 Step 2 from Lab Manual, Copyright 2023 StudeerSnel B.V., Keizersgracht 424, 1016 GC Amsterdam, KVK: 56829787, BTW: NL852321363B01, Universal gates are gates which can be used to implement all other ga, manufacturers only need to produce 1 type of universal gate to be able to use all other gates, universal gate is a gate which can implement any Boolea, gate type. endstream endobj 298 0 obj<> endobj 300 0 obj<>/Font<>/ProcSet[/PDF/Text]/ExtGState<>>>>> endobj 301 0 obj<> endobj 302 0 obj<> endobj 303 0 obj<> endobj 304 0 obj[/ICCBased 318 0 R] endobj 305 0 obj<> endobj 306 0 obj<> endobj 307 0 obj<> endobj 308 0 obj<> endobj 309 0 obj<>stream 0

Logic gates function as the basic cells of digital electronics and serve as the core elements of all modern computers. To So we went ahead and created two 2 of the input XOR gates. Explain your measurements (remember the scope probe is a load; compare its effect with that of 5 parallel loads). Exceeding the specified maximum fan-out (or load) may cause a malfunction because the circuit cannot supply the power demanded from it. - Understanding how to construct any combinational logic function using NAND or NOR gates only. 0000002840 00000 n

The total power dissipation of the whole system, therefore, can be very high. followed by an inverter not the other way around. Question 3: What values are you adding? 0000004856 00000 n Propagation delay is the time delay for a signal transition to propagate from input to output when the binary input signals change in value. 0 0 0 0 0 0 o7qwztie|I7RHEPf?)FUp`k>a;|. k-70o89*)`Q*`a^0aL - 2`R,/n?c!Q!OXSw 5hNn 6(4?- A'k A standard load is usually defined as the amount of current needed by an input of another gate in the same logic family. Draw an input versus output curve with the input ranging from 0V to 5V. 5 shows a two-input CMOS NAND gate circuit. 0000002272 00000 n TTL ICs are usually distinguished by numerical designation as the 5400 and 7400 series. Our goal is to make the OpenLab accessible for all users. Understand the concept of Universal Gates (NAND & NOR)

It should be noted that the transition period for the rising and falling edges of the same gate may not necessarily be the same, although it is normally desirable to have a symmetrical transition. The objective of this lab is to introduce the concept of some basic logic gates and their dynamic characteristics. Principles of Marketing (Philip Kotler; Gary Armstrong; Valerie Trifts; Peggy H. Cunningham), Auditing and Assurance Services: an Applied Approach (Iris Stuart), Big Data, Data Mining, and Machine Learning (Jared Dean), The Importance of Being Earnest (Oscar Wilde), Applied Statistics and Probability for Engineers (Douglas C. Montgomery; George C. Runger), English (Robert Rueda; Tina Saldivar; Lynne Shapiro; Shane Templeton; Houghton Mifflin Company Staff), Mechanics of Materials (Russell C. Hibbeler; S. C. Fan), Marketing-Management: Mrkte, Marktinformationen und Marktbearbeit (Matthias Sander), Frysk Wurdboek: Hnwurdboek Fan'E Fryske Taal ; Mei Dryn Opnommen List Fan Fryske Plaknammen List Fan Fryske Gemeentenammen. 0000002673 00000 n WebLab Work: (All Lab work must be shown in the Lab report) For the following logic gates, verify the logic operation each gate performs: a. Use of switches as inputs and light emitting diodes (LEDs) or LCD (liquid crystal PK ! Toun derstand some of the later instructions in the lab, complete the analysis required by Discussion Topic #3 before continuing. Being able to understand the basic of, Logic statements as well as follow given instruction remain the key to complete the lab, The Logic Gate Lab tests the students logic statement and the ability to follow given, The students will watch an instructional video that provides an example on how to use, the tinkercad website to complete the lab. 0000000933 00000 n Combinational logic requires the use of two or more gates to form a useful, complex function. ECL is used only in systems requiring high-speed operation. 6 shows a CMOS transmission gate circuit. 0000019016 00000 n 0000008325 00000 n

In fact, an AND gate is typically implemented as a NAND gate

Input B 0 1 0 1. will explore FPGA resources utilized to develop logic in hardware. WebAND, NOT and OR gates are the. Most logic gates have two inputs and one output. Sometimes, the term loading is used instead of fan-out. Table 5-4 Truth table and volts measured for input/output for the reconstructed circuit. Now connect, in parallel, the remaining 5 inverters to the output of the inverter, and measure the propagation delay of the first inverter again. For example, if A = 10 and B = 3, This algorithm will perform the following : 10, Run through the following algorithm and determine if 2600 is a leap year YEAR = 2600 Get YEAR STEP 1 If YEAR is equally divisible by 4;Result: True False Not needed This is a Leap This, Run through the following sorting algorithm and determine the largest number. Now we will look at the operation of each. 0000002876 00000 n

Both input and output signals are not ideal signals, i.e. NOR Gate 7 VIII. WebLab 2 6 4. %%EOF The AND, OR, NAND, and NOR gates can be extended to have more than two inputs. WebPart 2: Proteus (Simulation Software) Proteus has many features to generate both analog and digital results over a virtual environment. Procedure : 1. 297 0 obj<> endobj 519 31 Now. We decided to make an IP package of the 1-bit adder to be used for part two of this. 0000001788 00000 n New York City College of Technology | City University of New York. 0T\N-U9xgsb&. Introduce students to the tools, facilities and components needed for the experiments in digital To start this lab, we had to, create 3 of the 2-input AND gates that would be connected to the 3 input OR gate which needed to be, created. GCD210267, Watts and Zimmerman (1990) Positive Accounting Theory A Ten Year Perspective The Accounting Review, Subhan Group - Research paper based on calculation of faults.

The universality of the NAND and NOR gates means that they can be used as an inverter and the combinations of NAND/NOR gates can be used to implement the AND, OR, and all other logic operations. followed by an inverter not the other way around.

2. 0 0 1 0 0 0 The inputs for this particular XOR gate would be X, Y, Cin. Consider Discussion Topic #4 before continuing. Include Boolean algebra, truth tables, and logic diagrams for the circuit reconstructed with only NAND gates. Basic Gates 3 IV. 2-input AND gate b. Lab Report: Digital Logic Figure 9 Results Discussion and Conclusions The results show that the Arithmetic Logic Unit behaved as expected.

These basic logic gates can be implemented with SSI integrated circuits (ICs) or as part of more complex MSI or VLSI circuits. A truth table is a table showing all possible values at the inputs of a digital circuit and the corresponding value of the output. %%EOF The simulation will test the 8 possible combinations for x, y and c_in. %PDF-1.4 % This is useful as The truth table they have finite rise and fall times (see Fig. Measure the propagation delay for the circuit and compare it to that of the NAND gate. h word/document.xml}n}B662h,^;!q88Iek98zs9`I$r3VDQH'eRccGlw(?mM6cR5P/L\xon}u ,?s|GT]7T@OO9e9*}X_Ig=-q g%{=r`(i3X6#$8{g" B?&Fc

WebExperiment 1 - Basic Logic Gates with Logisim Objectives: 1. 2). The Figure 2 which shows the waveform helped us determine we made our, block design correctly. 2.0V to 5.0V = Logic 1 and lights the H indicator. Now change the control signal to a 50Hz bipolar input (+5V, -5V). Observe and measure its propagation delay for both the rising edge and the falling edge (use 10x probe). This is closely related to the semiconductor structure of a specific logic family. 0000007220 00000 n

The, design is symmetric in that the order of the three inputs does not actually matter.

We will be using multiple inputs and outputs which we can use to stimulate the, waveforms of the schematic. endstream endobj 520 0 obj<>/OCGs[524 0 R]>>/PieceInfo<>>>/LastModified(D:20080418223301)/MarkInfo<>>> endobj 522 0 obj[523 0 R] endobj 523 0 obj<>>> endobj 524 0 obj<>/PageElement<>>>>> endobj 525 0 obj<>/ProcSet[/PDF/Text]/ExtGState<>/Properties<>>>/StructParents 0>> endobj 526 0 obj<> endobj 527 0 obj<> endobj 528 0 obj<> endobj 529 0 obj<> endobj 530 0 obj<> endobj 531 0 obj<> endobj 532 0 obj<> endobj 533 0 obj<> endobj 534 0 obj<> endobj 535 0 obj<>stream

There are two types of noise to be considered.

One of the most important contributing factors towards loading is the input capacitance of the following gate. t(%@

There are two functions required to observe and F1 is in the Observations: Truth Tables 1= On = High 0 = Off = Low Lab 6 Gate: Lab # / Name Lab 6 (AND Gate) Input A 0 0 1 1.

Theory: AND, OR, NOT are called basic gates as their logical operation cannot be simplified further. Universal gates are gates which can be used to implement all other gates. 0000004299 00000 n The lab consists, of 4 problems that will be completed on tinkercad.com.

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%%EOF The NAND and NOR gates are universal gates.

1) Find the Boolean equation for the logic circuit shown in Figure 5-4. 521 0 obj<>stream This parameter does not include the power delivered from another gate. NAND and NOR gates are economical and easier to fabricate and are the basic gates used in all Power dissipation is an important parameter. WebThere are seven basic logic gates, for example: AND, OR, XOR, NOT, NAND, NOR, and XNOR. 0000001427 00000 n